In general, non-volatile memory devices are memory devices that will retain stored data even while power is off. Typically, non-volatile memory devices are utilized in various products and devices, such as mobile telecommunication devices, memory cards, smart cards, and other devices and applications where power is not always available, frequently interrupted and/or when lower power usage is required. In general, non-volatile memory devices include, for example, EPROM (Erasable and Programmable Read Only Memory) devices, EEPROM (Electrically Erasable and Programmable Read Only Memory) devices, SRAM and Flash Memory. More specifically, one type of non-volatile memory is known as split-gate, floating gate, EEPROM memory devices. These split-gate transistor memory devices are typically employed in various applications, particularly embedded systems, as such memory devices afford low cost, in system re-programmable, and highly reliable non-volatile memory solutions.
FIG. 1A illustrates a cross-sectional view of a conventional non-volatile split-gate memory device (10). In particular, FIG. 1A depicts a pair of split-gate memory cells M1 and M2 formed on a p-type semiconductor substrate layer (11). A plurality of n-type diffusion regions (12) and (13) are formed in the substrate (11). The diffusion region (12) is a common source region (12) that is shared by cells M1 and M2, and the diffusion regions (13) are drain regions. The memory cells M1 and M2 have mirror image structures with respect to the common source region (12). In particular, each cell M1, M2 comprises a channel region (14) between the common source region (12) and drain regions (13), a floating gate (15), a control gate (16), a gate insulation layer (17), a polyoxide layer (18) formed on the floating gate (15), and a tunnel insulating layer (19).
The floating gate (15) is an electrically isolated gate electrode, which is formed to overlap a portion of the channel region (14) and a portion of the common source region (12). The control gate (16) is formed to overlap a portion of the channel (14) adjacent the drain region (13), as well as overlap a sidewall and upper portion of the floating gate (15). The gate insulating layer (17) is formed over the substrate (11) to insulate the floating gate (15) and control gate (16) from the substrate (11). The polyoxide layer (18) is formed on the floating gate (15) by a local oxidation of silicon (LOCOS) process. The tunnel insulating layer (19) is disposed between the floating gate (15) and control gate (16), and covers one sidewall of the floating gate (15) and a portion of the channel region (14).
In one conventional design, each control gate (16) is a word line that extends in a row direction (orthogonal to the plane of the drawing page) and commonly connected to each memory cell along the rows. An interlayer dielectric layer (20) is formed over the memory cells M1, M2. A common source line (22) is patterned from a 1st level metallization layer and connected to the common source region (12) by a contact plug (21). The common source line (22) extends in the same direction as the wordlines (or control gates (16)). The drain regions (13) are connected by a common bit line (not shown) that is formed from a second metallization layer and which extends orthogonal to the row direction. Each pair of rows that share a common source form a page.
In general, the memory cells MI and M2 are set to logical “1” or “0” depending on the charge stored in the respective floating gate electrodes (15). In particular, the floating gates (15) are used to change the threshold voltage of the memory cell transistor such that depending on the charge stored on the floating gate (15), the memory cell transistor is either in a high threshold state (non-conducting state) or a low threshold state (conducting state), wherein the conducting or non-conducting state is output as the logic level during a read operation.
In effect, each memory cell transistor is formed of a series connected memory transistor and a read/select transistor, wherein the memory transistor is formed by the floating gate (15) and portion of the channel (14) adjacent to, and overlapped by, the floating gate (15), and wherein the read/select transistor is formed by the control gate (16) and portion of the channel (14) adjacent to, and overlapped by, the control gate (16). The current flow through the channel (14) is controlled by the combination of the memory and read/select transistors, wherein the floating gate (15) essentially operates as an ON/OFF switch for the select/read transistor depending on the logical state of the memory cell.
In particular, in a programmed state (high threshold state), an excess of electrons are stored on the floating gate electrode (15). The memory cells M1 and M2 are programmed to a high threshold voltage using a technique know as CHE (Channel Hot Electron) SSI (source side injection) to inject electrons flowing in the channel (14) into the floating gate (15) through the gate insulating layer (17). These hot channel injected electrons are trapped on the floating gate electrode (15) and create a net negative voltage on the floating gate (15), which results in an increase in the threshold voltage required to change the memory cell from a non-conducting to a conducting state. During a read operation, the negatively charged floating gate (15) opposes an electric field created by a positive voltage applied to the control gate (16) of the read/select transistor. In effect, a programmed memory cell is in a non-conducting state because source-drain current does not flow when normal read/select control voltages are applied to the control gate (16) during a read operation.
On the other hand, in a non-programmed state (low threshold state), the floating gates (15) are devoid of negative charge (as compared to the programmed state). In particular, during an erase process, electrons on the floating gate (15) are transferred to the control gate (16) through the tunnel oxide layer (19) using a technique known as Fowler-Nordheim (FN) tunneling. When the memory cell is erased, the floating gate (15) is discharged to have a net positive charge that allows the memory cell transistor to be turned “ON” or “OFF”, depending on the voltage on the control gate (16). When the memory cell is erased, a positive voltage on the floating gate (15) causes the portion of the channel (14) under the floating gate (15) to become inverted. In the non-programmed state, however, current flow in the channel (14) will be controlled by the voltage applied to the control gate (16).
FIG. 1B is a table that illustrates conventional operating conditions for the memory cells M1 and M2 during erase, program, and read operations. In the conventional scheme depicted in FIG. 1B, a read voltage is set to 1.8 volts. The threshold voltage Vth for an “ON” (low threshold/non-programmed) memory cell is within a range of about −0.5V to 0.8V, and the Vth for an “OFF” (high threshold/programmed) memory cell is about 3.2V to about 4.7V.
FIG. 1B illustrates operating voltages for performing a read operation. During a read cycle, the read voltage of 1.8 V is applied to the control gate (16) (word line), 0V is applied to both the source (12) and substrate (11), and a voltage of 0.8V is applied to the drain region (13) (bit line). Under these conditions, if the selected memory cell is in the “high threshold” or “OFF” state, the memory transistor will not conduct. The lack of current flowing through the selected bit line will be detected and output as a logic “0”. On the other hand, if the selected memory cell is in the “low threshold” or “ON” state, then the memory transistor will conduct. The current, flowing through the selected bit line, will be detected and output as a logic “1”.
FIG. 1B illustrates the operating voltages for an erase process to discharge the floating gate (15). During an erase process, the drain (13), source (12) and substrate (11) are set to 0V and a predetermined voltage (12V or greater) is applied to the control gate (16). The high voltage on the control gate (16) creates a strong electric field that initiates FN tunneling, such that electrons in the floating gate (15) are transferred from the floating gate (15) to the control gate (16) through the tunnel insulating layer (19). During erasing, an strong electric field is concentrated at an acute region (15a) (see, FIG. 1A) formed at a rim of the floating gate (15), and the FN tunneling occurs at the vicinity of such acute region (15a). As negative charge is transferred from the floating gate (15) and positive charge accumulates on the floating gate (16), the FN tunneling mechanism will continue until there is insufficient voltage across the tunnel oxide (19) to sustain the FN tunneling mechanism. As noted above, the positive charge on the floating gate (15) places the memory cell into a “low threshold” state, allowing the cell to conduct during a read operation (and thus being read as a logical “1”).
FIG. 1B further illustrates operating voltages for a program operation. As noted above, the memory cells M1, M2 are programmed by source side channel hot electron injection. During programming, a voltage of 1.5V is applied to the control gate (16), which is sufficient to activate the channel (14) under the control gate (16). Furthermore, a voltage of 0.5V is applied to the drain (13), a voltage of 0V is applied to the substrate (11), and a relatively large source voltage of 9V is applied to the source (12) via the source line (22). The source-to-drain voltage differential generates channel hot electrons. The source voltage is capacitively coupled to the floating gate (15) via capacitance C1, which creates an electric field between the floating gate (15) and the channel (14). As the electrons flow from the drain (13) to the source (12) and gain kinetic energy, the path of such electrons is altered by the electric field between the floating gate and substrate. Those electrons with sufficient energy to overcome the substrate-gate oxide (Si—SiO2) barrier will accelerate from the channel (14) toward the floating gate electrode (15) through the gate oxide (17), and be trapped on the floating gate electrode (15). As negative charge accumulates on the floating gate (15), the positive charge generated during an erasing process is neutralized, and the hot channel electron injection will continue until there is insufficient voltage differential to sustain the injection mechanism. As noted above, the negative charge on the floating gate (15) places the memory cell into a “high threshold” state, preventing the cell to conduct during a read operation (and thus being read as a logical “0”).
Although the conventional split-gate memory framework of FIG. 1A provides advantages over other conventional non-volatile memory designs, the split-gate framework of FIG. 1A can suffer performance problems with respect to data retention and cycling endurance. For instance, as noted above, an erase operation requires application of a high-voltage (e.g., 12V or greater) to the control gate (16) to initiate tunneling through the tunneling oxide (19) from the floating gate (15) to the control gate (16). Over time, the continuous application of such high voltage to the control gate (16) can adversely affect and stress the dielectric material of the tunneling layer (19) causing defects that can lead to unpredictable device reliability, especially for thin tunneling oxide layers.
Moreover, with respect to programming, although source side hot channel injection is a highly efficient programming technique, the conventional split gate memory framework of FIG. 1A affords a relatively low degree of capacitive coupling between the source (12) and the floating gate (15). In particular, as depicted in FIG. 1A, the coupling ratio C1 is limited by the overlapping area between the common source (12) and the floating gate (15). An increased coupling ratio yields increased programming speed. In the conventional design, a relatively large source voltage of 9V must be applied to the source region to effectively increase the coupling ratio by increasing the lateral diffusion of the source region (12).
However, a large source voltage applied to the source region (12) can result punch-through and junction breakdown due an increase of a source depletion region (12a). Indeed, the increased lateral diffusion of the source depletion region (12a) can result in punch through near the source region (12) due to excessive current. As the conventional framework of FIG. 1A is scaled to smaller design rules, the ability to use large source voltages is limited as the required gap X1 margin decreases.